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single - supply, differential 18 - bit adc driver ada4941 - 1 rev. c information furnished by analog devices is believ ed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no lic ense is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781 .329.4700 www.analog.com fax: 781.461.3113 ? 2006 C 2011 analog devices, inc. all rights reserved. features single - ended - to - differential co nverter excellent l inearity distortion ? 110 dbc @100 khz for v o , dm = 2 v p - p low n oise : 10.2 nv/ hz , output - referred , g = 2 extremely low p ower : 2. 2 ma (3 v supply) high input imp edance : 24 m ? user - adjustable gain h igh s peed : 31 mhz, ? 3 db b andwidth (g = +2) fast settling t ime : 300 ns to 0.005% for a 2 v step low o ffset : 0.8 mv max, o utput - r eferred, g = 2 rail - to - rail o utput disable feature wide supply voltage r ange : 2.7 v to 12 v available in space - saving, 3 mm 3 mm lfcsp applications single - s upply data acquisition s ystems instrumentation process c ontrol battery - power s ystems medical i nstrumentation functional block dia gram dis 4 3 2 1 in out? out+ v+ ref fb v? 7 8 5 6 05704-001 figure 1. soic/lscsp pinout ?60 ?140 0.1 10 1 1000 frequency (khz) distortion (dbc) 100 v o = 2v p-p v o = 6v p-p 05704-045 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?1 10 ? 1 15 ?120 ?125 ?130 ?135 hd3 hd2 hd3 hd2 figure 2 . distortion vs. frequency at various output amplitudes general description the ada4941 - 1 is a low power, low noise differ ential driver for adcs up to 18 bits in systems that are sensitive to power. the ada4941 - 1 is configured in an easy - to - use, single - e nded - to - differential configuration and requires no external components for a gain of 2 configuration. a resistive feedback network can be added to achieve gains greater than 2 . the ada4941 - 1 provides essential benefits , such as low distortion and high snr , that are required for driving high resolution adcs. with a wide input voltage range (0 v to 3.9 v on a single 5 v supply), rail - to - rail output, high input impedance , and a user - adjustable gain , the ada4941 - 1 is designed to drive single - supply adcs with di fferential inputs found in a variety of low power applications, including battery - operated devices and single - supply data acquisition systems. the ada4941 - 1 is ideal for driving the 16 - bit and 18 - bit pulsar ? adcs such as the ad7687, ad7690, and ad7691. th e ada4941 - 1 is manufactured on adis proprietary second - generation xfcb process , which enables the amplifier to achieve 18 - bit performance on low supply currents. the ada4941 - 1 is available in a small 8 - lead lfcsp as well as a standard 8 - lead soic and is r ated to work over the extended industrial temperature range, ? 40 c to +125 c.
ada4941- 1 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 15 basic operation .......................................................................... 15 dc error calculations ............................................................... 16 output voltage noise ................................................................. 17 frequency response vs. closed - loop gain ........................... 19 applications ..................................................................................... 20 overview ..................................................................................... 20 using the ref pin ...................................................................... 20 internal feedback network power dissipation ...................... 20 disable feature ........................................................................... 20 adding a 3 - pole, sallen - key filter ........................................... 21 driving the ad7687 adc ........................................................ 22 gain of ?2 configuration .......................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 8 / 11 rev . b to rev. c change to g ain error drift unit, table 1 ...................................... 3 change to g ain error drift unit, table 2 ...................................... 4 change to g ain error drift unit, table 3 ...................................... 5 8 /10 rev. a to rev. b added caption to figure 1 .............................................................. 1 added exposed pad not ation to figure 4 and table 6 ................ 7 added expo sed pad notation to outline dimensions ............. 23 changes to ordering guide .......................................................... 23 3/09 rev. 0 to rev. a change to g ain error drift parameter, table 1 ............................ 3 change to g ain error drift parameter, table 2 ............................ 4 change to g ain error drift parameter, table 3 ............................ 5 updated outline dim ensions ....................................................... 23 4 /0 6 revision 0 : initial version
ada4941- 1 rev. c | page 3 of 24 specifications t a = 25c, v s = 3 v, out+ connected to fb (g = 2) , r l , dm = 1 k ?, ref = 1.5 v, unless otherwise noted. table 1 . parameter conditions min typ max unit dynamic performance ?3 db bandwidth v o = 0.1 v p -p 21 30 mhz v o = 2.0 v p -p 4.6 6.5 mhz overdrive recovery time +recover/ ? recovery 320 /650 ns slew rate v o = 2 v step 22 v/s settling time 0.005% v o = 2 v p - p step 300 ns noise/distortion performance harmonic distortion f c = 40 khz, v o = 2 v p -p, hd2/hd3 ? 116/ ? 112 dbc f c = 100 khz, v o = 2 v p - p, hd2/hd3 ? 101/ ? 98 dbc f c = 1 mhz, v o = 2 v p -p, hd2/hd3 ? 75/ ? 71 db c rto voltage noise f = 100 khz 10.2 nv/hz input current noise f = 100 khz 1. 6 pa/hz dc performance differential output offset voltage 0.2 0.8 mv differential input offset voltage drift 1.0 v/c single - ended input offset voltage amp a1 or amp a2 0.1 0.4 mv single - ended input offset voltage drift 0.3 v/c in put bias current in and ref 3 4.5 a input offset current in and ref 0.1 a gain (+out ? ?out)/(in ? ref) 1.98 2 .00 2.01 v/v gain error ? 1 +1 % gain error drift 1 5 ppm /c input characteristics input resistance in and ref 24 m? input c apacitance in and ref 1.4 pf input common - mode voltage range 0.2 1.9 v common - mode rejection ratio (cmrr) cmrr = v os, dm /v cm , v ref = v in , v cm = 0.2 v to 1.9 v , g = 4 81 105 db output characteristics output voltage swing each single - ended outp ut , g = 4 2.9 0 2.95 v output current 25 ma capacitive load drive 2 0% overshoot , v o , dm = 200 mv p -p 20 pf power supply operating range 2.7 12 v quiescent current 2.2 2.4 ma quiescent current disable 10 16 a power supply rejection ratio (psrr) +psrr psrr = v os, dm / v s , g = 4 86 100 db ?psrr 86 110 db disable dis input voltage disabled , dis = high 1.5 v enabled , dis = low 1.0 v dis input current disabled , dis = high 5.5 8 a enabled , dis = low 4 6 a turn - on time 0.7 s turn - off time 30 s
ada4941- 1 rev. c | page 4 of 24 t a = 25c, v s = 5 v, out+ connected to fb (g = 2) , r l, dm = 1 k?, ref = 2.5 v, unless otherwise noted. table 2 . parameter conditions min typ max unit dynamic performance ?3 db bandwidth v o = 0.1 v p -p 22 31 mhz v o = 2.0 v p -p 4.9 7 mhz overdrive recovery time +recover/ ? recovery 200/600 ns slew rate v o = 2 v step 24.5 v/s settling time 0.005% v o = 6 v p - p step 610 ns noise/distortion performance harmonic distortion f c = 40 khz, v o = 2 v p -p, hd2/hd3 ? 118/ ? 119 dbc f c = 100 khz, v o = 2 v p -p, hd2/hd3 ? 110/ ? 112 dbc f c = 1 mhz, v o = 2 v p -p, hd2/hd3 ? 83/ ? 73 db c rto voltage noise f = 100 khz 10.2 nv/hz input current noise f = 100 khz 1.6 pa/hz dc performance differential output offset voltage 0.2 0.8 mv differential input offset voltage drift 1.0 v/c single - ended input offset voltage amp a1 or amp a2 0.1 0.4 mv single - ended input offset voltage drift 0.3 v/c input bias current in and ref 3 4.5 a input offset current in and ref 0.1 a gain (+out ? ?out)/(in ? ref) 1.98 2 2.01 v/v gain error ? 1 +1 % gain error drift 1 5 p pm /c input characteristics input resistance in and ref 24 m? input capacitance i n and ref 1.4 pf input common - mode voltage range 0.2 3.9 v common - mode rejection ratio (cmrr) cmrr = v os, dm /v cm , vref = vin, v cm = 0.2 v to 3.9 v, g = 4 84 106 db output characteristics output voltage swing each single - ended output , g = 4 4 .85 4.93 v output current 25 ma capacitive load drive 20% overshoot, v o , dm = 200 mv p -p 20 pf power supply operating range 2.7 12 v quiescent current 2.3 2.6 ma quiescent current disable 12 20 a power supply rejection ratio (psrr ) +psrr psrr = v os, dm /v s , g = 4 87 100 db ?psrr 87 110 db disable dis input voltage disabled, dis = high 1.5 v enabled, dis = low 1.0 v dis input current disabled, dis = high 5.5 8 a enabled, dis = low 4 6 a turn - on tim e 0.7 s turn - off time 30 s
ada4941- 1 rev. c | page 5 of 24 t a = 25c, v s = 5 v, out+ connected to fb (g = 2) , r l, dm = 1 k?, ref = 0 v, unless otherwise noted. table 3 . parameter conditions min typ max unit dynamic performance ?3 db bandwidt h v o = 0.1 v p -p 23 32 mhz v o = 2.0 v p -p 5.2 7.5 mhz overdrive recovery time +recover / ? recovery 200/650 ns slew rate v o = 2 v step 26 v/s settling time 0.005% v o = 12 v p - p step 980 ns noise/distortion performance harmonic distortion f c = 40 khz, v o = 2 v p -p, hd2/hd3 ? 118/ ? 119 dbc f c = 100 khz, v o = 2 v p -p, hd2/hd3 ? 109/ ? 112 dbc f c = 1 mhz, v o = 2 v p -p, hd2/hd3 ? 84/ ? 75 db c rto voltage noise f = 100 khz 10.2 nv/hz input current noise f = 100 khz 1.6 pa/hz dc perfor mance differential output offset voltage 0.2 0.8 mv differential input offset voltage drift 1.0 v/c single - ended input offset voltage amp a1 or amp a2 0.1 0.4 mv single - ended input offset voltage drift 0.3 v/c input bias current in and ref 3 4.5 a input offset current in and ref 0.1 a gain (+out ? ?out)/(in ? ref) 1.98 2 2.01 v/v gain error ? 1 +1 % gain error drift 1 5 ppm /c input characteristics input resistance in and ref 24 m? input capacitance in and ref 1.4 pf input common - mode voltage range ?4.8 +3.9 v common -mo de rejection ratio (cmrr) cmrr = v os, dm /v cm , vref = vin, v cm = ?4.8 v to +3.9 v, g = 4 85 105 db output characteristics output voltage swing each single - ended output , g = 4 v s ? 0.25 v s 0.14 v output current 25 ma capacitive load drive 20 % overshoot, v o , dm = 200 mv p -p 20 pf power supply operating range 2.7 12 v quiescent current 2.5 2.7 ma quiescent current disable 15 26 a power supply rejection ratio (psrr) +psrr psrr = v os, dm /v s , g = 4 87 100 db ?psrr 87 1 10 db disable dis input voltage disabled, dis = high ?3 v enabled, dis = low ?4 v dis input current disabled, dis = high 7 10 a enabled, dis = low 4 6 a turn - on time 0.7 s turn - off time 30 s
ada4941- 1 rev. c | page 6 of 24 absolute maximum rat ings table 4 . parameter rating supply voltage 12 v power dissipation see figure 3 storage temperature range ? 65c to +125c operating temperature range ? 40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, ja is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad (if applicable) on the pcb surface that is thermally connected to a copper plane, with zero airfl ow. table 5 . thermal resistance package type ja jc unit 8 - lead soic on 4 -l ayer b oard 126 28 c/w 8 - lead lfcsp with ep on 4 -l ayer b oard 83 19 c/w maximum power dissipation the maximum safe power dissipation in the ad a4941 - 1 pa ckage is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresse s that the package exerts on the die, permanently shifting the parametric performance of the ad a4941 - 1. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices potentially causing failure. the power d issipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. the power dissipated due to all of the loads is equal to the sum of the power dissipation due to each individual load. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact wit h the package leads from metal traces, through holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a copper plane to achieve the spe cified ja . figure 3 shows the maximum safe power dissipation in the packages vs. the ambient temperature for the 8 - lead soic ( 126 c/w) and for the 8 - lead lfcsp (83 c/w) on a jedec standard 4 - layer board . the lfcsp must have its underside paddle soldered to a pad that is thermally connected to a pcb plane. ja values are approximations. 2.5 0 ?40 120 ambient temperature (c) maximum power dissipation (w) 2.0 1.5 1.0 0.5 ?20 0 20 40 60 80 100 lfcsp soic 05704-002 figure 3 . maximum power dissipation vs. temperature for a 4 - layer board esd caution esd (electrostatic discharge) se nsitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ada4941- 1 rev. c | page 7 of 24 pin configuration an d function descripti ons dis 4 3 2 1 in out? out+ notes 1. the exposed p ad is not electrical l y connected t o the device. it is typical l y soldered t o ground or a power plane on the pcb th a t is thermal l y conductive. v+ ref fb v? 7 8 5 6 05704-101 figure 4 . pin confi guration table 6 . pin function description s pin no. mnemonic description 1 fb feedback input 2 ref reference input 3 v+ positive power supply 4 out+ non i nverting output 5 out? inverting output 6 v? negative power supply 7 dis disable 8 in input ep (for lfcsp only) exposed paddle. the exposed pad is not electrically connected to the device. it is typically soldered to ground or a power plane on the pcb that is thermally conductive.
ada4941- 1 rev. c | page 8 of 24 typical performance characteristics unl ess otherwise noted, v s = 5 v, r l, dm = 1 k?, ref = 2.5 v, dis = low , out+ directly connected to fb (g = 2) , t a = 25c. 2 ?16 ?15 ?14 ?13 ?12 1 1000 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 10 100 v o, dm = 0.1v p-p v s = +3v v s = +5v v s = 5v 05704-004 figure 5. small signal frequency response for various power supplies 2 ?16 ?15 ?14 ?13 ?12 1 1000 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 10 100 +25c ?40c +85c v o, dm = 0.1v p-p 05704-005 figure 6. small signal frequency response at various temperatures 2 ?15 1 1000 frequency (mhz) normalized closed-loop gain (db) 10 100 r l, dm = 1k ? r l, dm = 5k ? r l, dm = 500 ? 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 ?1 1 ?12 ?13 ?14 v o, dm = 0.1v p-p 05704-006 figure 7. small signal frequency response for various resistive loads 2 ?16 ?15 ?14 ?13 ?12 0.1 100 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 1 10 v s = +3v v o, dm = 2v p-p v s = +5v v o, dm = 6v p-p v s = 5v v o, dm = 12v p-p 05704-007 figure 8. large signal frequency response for various power supplies 2 ?16 ?15 ?14 ?13 ?12 0.1 100 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 1 10 +25c ?40c +85c v o, dm = 6v p-p 05704-008 figure 9. large signal frequency response at various temperatures 2 ?16 0.1 10 frequency (mhz) normalized closed-loop gain (db) r l, dm = 1k ? r l, dm = 5k ? r l, dm = 500 ? v o, dm = 6v p-p 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 ?1 1 ?12 ?13 ?14 ?15 1 05704-009 figure 10 . large signal frequency response for various resistive loads
ada4941- 1 rev. c | page 9 of 24 2 ?16 ?15 ?14 ?13 ?12 1 100 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 10 g = +4 g = +10 g = +2 g = ?2 v o, dm = 0.1v p-p 05704-010 figure 11 . small signal frequency response for various gains 2 ?16 ?15 ?14 ?13 ?12 1 100 10 1000 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 c l = 0pf c l = 20pf v o, dm = 0.1v p-p 05704-011 figure 12 . small signal frequency response for various capacitive loads 2 ?16 ?15 ?14 ?13 ?12 1 10 1000 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 vref = 0.05v p-p v s = +5v v s = 5v v s = +3v 05704-012 figure 13 . ref input small signal frequency response for various supplies 2 ?16 ?15 ?14 ?13 ?12 1 10 1000 frequency (mhz) normalized closed-loop gain (db) 1 0 ?1 ?2 ?3 ?1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 100 g = +4 g = +10 g = +2 g = ?2 v o, dm = 2v p-p 05704-013 figure 14 . large signal frequency response for various gains 2 ?16 ?15 ?14 ?13 ?12 0.1 10 1 1000 frequency (mhz) normalized gain (db) 1 0 ?1 ?2 ?3 ? 1 1 ?4 ?5 ?6 ?7 ?8 ?9 ?10 100 v o, dm = 2v p-p v o, dm = 6v p-p v o, dm = 0.1v p-p 05704-014 figure 15 . frequency response for various output amplitudes ?70 ?140 0.1 10 1 1000 frequency (khz) distortion (dbc) 100 05704-015 hd3 hd2 hd2 r l = 2k ? r l = 1k ? r l = 500? v o, dm = 2v p-p vref = midsupply ?80 ?90 ?100 ?1 10 ?120 ?130 figure 16 . distortion vs. frequency for various loads
ada4941-1 rev. c | page 10 of 24 ? 65 ?75 ?85 ?95 ?105 ?115 ?125 ?135 020 output amplitude (v p-p) distortion (dbc) 05704-016 v s = +5v f = 10khz v s = 5v v s = +3v 24681012141618 hd2 hd2 hd2 hd3 hd3 hd3 figure 17. distortion vs. output amplitude for various supplies (g = +2) ? 60 ?140 0.1 10 1 1000 frequency (khz) distortion (dbc) 100 05704-017 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 ?135 hd3 hd3 hd2 v s = +3v v s = +5v v s =5v hd2 v o, dm = 2v p-p vref = midsupply figure 18. distortion vs. frequency for various supplies ? 60 ?140 0.1 10 1 1000 frequency (khz) distortion (dbc) 100 v o = 2v p-p v o = 6v p-p 05704-045 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 ?135 hd3 hd2 hd3 hd2 figure 19. distortion vs. frequency at various output amplitudes hd3 ? 65 ?145 020 output amplitude (v p-p) distortion (dbc) 05704-019 differential g = ?2 f = 10khz 24681012141618 ?75 ?85 ?95 ?105 ?115 ?125 ?135 v s = +5v v s = 5v v s = +3v hd2 hd3 hd3 figure 20. distortion vs. output amplitude for various supplies (g = ?2) ? 70 ?140 0.1 10 1 1000 frequency (khz) distortion (dbc) 100 05704-020 hd3 hd3 hd3 g = ?2 g = +2 g = +4 v o, dm = 2v p-p vref = midsupply ?80 ?90 ?100 ?110 ?120 ?130 hd2 hd2 figure 21. distortion vs. frequency for various gains 0.12 ?0.12 output voltage (v) 50ns/div v out = 200mv p-p 0.08 0.04 0 ?0.04 ?0.08 c l =0pf c l = 20pf 05704-022 figure 22. small signal transient response for various capacitive loads
ada4941- 1 rev. c | page 11 of 24 0.12 ?0.12 output voltage (v) 50ns/div v out = 200mv p-p 0.08 0.04 0 ?0.04 ?0.08 v s = +3v v s = + 5v or v s = 5v 05704-018 figure 23 . small signal transient re sponse for various supplies 8 ?8 amplitude (v) v s = 5v v o, dm = 12v p-p v o, dm 2 v in error = 2 v in ? v o, dm 6 4 2 0 ?2 ?4 ?6 2.4 ?2.4 error (mv) 1 div = 0.005% 1.8 1.2 0.6 0 ?0.6 ?1.2 ?1.8 1s/div 05704-023 figure 24 . settling t ime (0.005%) , v s = 5 v 12 ?12 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 output voltage (v) 1s/div input 2 output 05704-024 figure 25 . input overdrive recovery, v s = 5 v 8 ?8 output voltage (v) 200ns/div v s = 5v v o, dm = 12v p-p v s = 2.5v v o, dm = 6v p-p v s = 1.5v v o, dm = 2v p-p 6 4 2 0 ?2 ?4 ?6 05704-021 figure 26 . large signal transient response for various supplies 9 1 amplitude (v) v s = +5v v o, dm = 6v p-p v o, dm 2 v in error = 2 v in ? v o, dm 8 7 6 5 4 3 2 1.2 ?1.2 error (mv) 1 div = 0.005% 0.9 0.6 0.3 0 ?0.3 ?0.6 ?0.9 1s/div 05704-026 figure 27 . settling time (0.005%) , v s = +5 v 8 ?8 output voltage (v) 1s/div 6 4 2 0 ?2 ?4 ?6 input 2 output 05704-027 figure 28 . input overdrive recovery, v s = +5 v
ada4941- 1 rev. c | page 12 of 24 0 ?1 10 0.001 1000 frequency (mhz) psrr (db) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0.01 0.1 1 10 100 +psrr ?psrr 05704-028 figure 29 . power supply rejection ratio vs. frequenc y 3.5 1.0 ?40 120 temperature (c) power supply current (ma) v s = 5v v s = +5v v pd = v s? v s = +3v 3.0 2.5 2.0 1.5 ?20 0 20 40 60 80 100 05704-029 figure 30 . power supply current vs. temperature 150 0 ?40 120 temperature (c) differential output offset (v) ?20 0 20 40 60 80 100 05704-030 125 100 75 50 25 v os _a1 10v v os _a2 = 3v v os _a1 = 3v v os _a2 = 5v v os _a1 = 5v v os _a2 = 10 v figure 31 . differential output offset voltage vs. temperature 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 ?40 120 temperature (c) output saturation voltage with respect to rail (v) ?20 0 20 40 60 80 100 05704-031 5 v supplies, positive rail +5 v supplies, positive rail 5 v supplies, negative rail +5 v supplies, negative rail +3 v supplies, positive rail +3 v supplies, negative rail figure 32 . output saturation voltage vs. temperature 2.5 ?0.5 0.6 2.0 disable input voltage with respect to v s? (v) supply current (ma) i cc @ v s = 5v i cc @ v s = +5v i cc @ v s = +3v 2.0 1.5 1.0 0.5 0 0.8 1.0 1.2 1.4 1.6 1.8 05704-032 figure 33 . power supply current vs. disable voltage 140 0 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 180 200 offset voltage (v) frequency 120 100 80 60 40 20 v os 1 mean = ?8v std. dev = 47v v os 2 mean = 11v std. dev = 20v no. of units = 611 05704-033 figure 34 . differential output offset distribution
ada4941- 1 rev. c | page 13 of 24 100 1 1 100m frequency (hz) differential output voltage noise (nv/ hz ) 10 10 100 1k 10k 100k 1m 10m 05704-034 figure 35 . differential output voltage noise vs. frequenc y 2.65 2.35 ?40 125 temperature (c) input bias current (a) v s = 5v v s = +5v v s = +3v 2.60 2.55 2.50 2.45 2.40 ?25 ?10 5 20 35 50 65 80 95 110 05704-035 figu re 36 . input bias current vs. temperature for various supplies 3.3 2.7 ?40 120 temperature (c) reference bias current (a) ?20 0 20 40 60 80 100 05704-036 3.2 3.1 3.0 2.9 2.8 reference i bias = 5v reference i bias = 3v reference i bias = 10 v figure 37 . ref input bias current vs. temperature 28 0 1 1m frequency (hz) input current noise (pa/ hz ) 26 24 22 20 18 16 14 12 10 8 6 4 2 10 100 1k 10k 100k 05704-037 figure 38 . input current noise vs. frequency 3.5 1.5 ?0.5 10.0 input voltage with respect to v s? (v) input bias current (a) 05704-038 3.0 2.5 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 v s = 5 v v s = + 5v v s = + 3v figure 39 . input bias current vs. input voltage 4.0 2.0 0 10.0 reference input voltage with respect to v s? (v) reference input bias current (a) 05704-039 3.5 3.0 2.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 v s = 5 v vref = vin v s = + 5v v s = + 3v figure 40 . ref input bias current vs. ref input voltage
ada4941- 1 rev. c | page 14 of 24 10 0 ?40 120 temperature (c) disabled supply current (a) ?20 0 20 40 60 80 100 05704-040 8 6 4 2 g = 4 r f = 1k? r l = dis = high v s = 5 v v s = +5 v v s = +3 v figure 41 . disable supply current vs. temperature for various supplies 500mv/div 40s/div v pd v o, dm 05704-041 figure 42 . disable assert time ?40 ?1 10 0.1 1000 frequency (mhz) isolation (db) ?50 ?60 ?70 ?80 ?90 ?100 1 10 100 vin = 50mv p-p 05704-042 figure 43 . disabled input - to- output isolation vs. frequency 14 0 0 10 disable input voltage with respect to v s? (v) disable input current (a) 12 10 8 6 4 2 1 2 3 4 5 6 7 8 9 v s = 5v 05704-043 figure 44 . disable input current vs. disable input voltage 500mv/div 40s/div v pd v o, dm 05704-044 figure 45 . disable de a ssert time 100 0.0001 0.001 100 frequency (mhz) impedance ( ?) vop von 10 1 0.1 0.01 0.001 0.01 0.1 1 10 05704-025 figure 46 . single - ended output impedance vs. frequency
ada4941- 1 rev. c | page 15 of 24 t heory of operatio n the ada4941 - 1 is a low power , single - ended input, differential output amplifier optimized for driving h igh resolution ad cs . figure 47 illustrates how the ada4941 - 1 is typically connected. the amplifier is composed of an uncommitted amplifier, a1, driving a precision inverter, a2. the negative input of a1 is brought out to p in 1 (f b), allowing for user - programmable gain. the inverting op amp, a2, provides accurate inversion of the output of a1, vop, producing the output signal von. 1k ? 1k ? r g r f r f || r g 500 ? a2 a1 ref in vref 2 8 4 5 fb out+ + ? vop 1 out? + ? von vin vg 05704-052 figure 47 . basic connections (power supplies n ot shown) the v oltage applied to the ref pin appears as the output common - mode voltage. n ote that the voltage applied to the ref pin does not affect the voltage at the out+ pin. because of this, a differential offset can exist between the outputs , while the desired output common - mode v oltage is present . for example, when vop = 3.5 v and von = 1.5 v, the output common - mode voltage is equal to 2.5 v, just as it is when both outputs are at 2.5 v. in the first case, the differential voltage (or offset) is 2.0 v , and in the latter case , the differential voltage is 0 v . when calculating output voltages, both differential and common - mode voltages must be considered at the same time to avoid undesired differential offsets. basic operation in figure 47, r g and r f form the exter nal gain - setting network . vg and vref are external ly applied voltages . v o , cm is defined as the output common - mode voltage and v o , dm is defined as the differential - mode output voltage . the following e quations can be derived from figure 47: g f g f r r vg r r vin vop 1 (1) ) ( 2 1 vref r r vg r r vin von g f g f (2) ) ( 2 2 1 ) ( 2 , vref r r vg r r vin von vop dm v g f g f o (3) vref von vop cm v o 2 , (4) when r f = 0 and r g is removed , e quation 3 simplifies to the following: v o , dm = 2( vin ) ? 2( vref ) (5) 1k ? 1k ? 4.99k ? 1k ? 825 ? 500 ? a2 a1 ref in 2 8 4 5 fb +5v ?5v v s+ v s? out+ + ? vop 1 3 6 out? + ? von vin 05704-053 figure 48 . dual supply, g = 2.4 , single - ended - to- differential amplifier figure 48 shows an example of a dual - supply connection . in this example, vg and vref are set to 0 v, and the external r f and r g network provides a no ninverting gain of 1.2 in a1 . this example takes fu ll advantage of the rail - to - rail output stage . the gain equation is vop ? von = 2.4( vin ) (6) the in - series, 825 ? resistor combined with p in 8 compensates for the voltage error generated by the input offset current of a1 . the linear output range of both a1 and a2 extends to within 200 mv of each sup ply rail, which allows a pe ak - to - peak differential out put voltage of 19.2 v on 5 v supplies. 1k ? 1k ? 500 ? a2 a1 ref in 2 8 4 5 fb +5v v s+ v s? out+ + ? vop 1 3 6 out? + ? von +2.5v vin 05704-054 figure 49 . single +5v supply, g=2 single - ended - to- differential amplifier figure 49 shows a single 5 v supply connection with a1 used as a unity gain follower . the 2.5 v at the ref pin sets the output common - mode voltage to 2.5 v. the transfer function is then vop ? von = 2( vin ) ? 5 v (7)
ada4941- 1 rev. c | page 16 of 24 in this case, t he linear output voltage is limited by a1 . on the low end, t he outpu t of a1 start s to saturate and show degraded linearity w hen vop approaches 200 mv . on the high end, the input of a1 become s saturated and exhibit s degraded l inearity when vin moves beyond 4 v ( within 1 v of vcc ) . this limits the linear differential output voltage in the circuit shown in figure 49 to about 7.6 v p - p. 1k ? 1k ? 665 ? 1.02k ? 402 ? 500 ? a2 a1 ref in 2 8 4 5 fb +5v v s+ v s? out+ + ? vop 1 3 out? + ? von vin +2.5v 6 05704-055 figure 50 . 5 v supply, g = 5, s ingle - ended - to- differential amplifier figure 50 shows a single 5 v supply connection for g = 5 . the r f and r g network sets the gain of a1 to 2.5, and the 2.5 v at the ref input provides a centered 2.5 v output common - mode voltage . the transfer function is then vop ? von = 5( vin ) ? 5 v (8) the output range limits o f a1 and a2 limit the differential output voltage of the circuit shown in figure 50 to a pproxima t ely 8.4 v p - p . dc error calculation s 1k ? 1k ? r g r f r s? in i bp? a2 i bn? a2 v os? a1 500 ? a2 a1 ref in 2 8 4 5 fb out+ + ? vop 1 out? + ? von v os? a2 r s? ref i bp? a1 i bn? a1 05704-056 figure 51 . dc error sources figure 51 shows the major contributions to the dc output voltage error . for each output, the total error voltage can be calculated u sing familiar op amp concepts . equation 9 expresses the dc voltage error present at the vop output. f bp s bp os g f r _a1 i _in r _a1 i _a1 v r r vop_error ) ( ) )( ( 1 (9) when using data from the specifications tables, it is often more expedient to use input offset current in place of the individual input bias currents w hen calculating errors . input offset current is defined as the magnitude of the difference between the two input bias currents . using this definition , each input bias current can be expressed in terms of the average of the two input bias current s, i b , and the input offset current, i os , as i b p, n = i b i os /2 . dc errors are minimized when r s = r f || r g . in this case, e quation 9 is reduced to ) || ( ) ( 1 g f s f os os g f r r r r i _a1 v r r vop_error equation 10 expresses the dc voltage error present at the von output. von_error = ?( vop_error ) + 2[ v os _a2 ? ( i bp _a2 )( r s _ref + 500)] + 1000( i bn _a2 ) (10) the internal 500 ? resistor is provided on - chip to minimize dc errors due to the input offset current in a2 . the minimum error is achieved when r s _ref = 0 ? . in this case, equation 10 is reduced to von_error = ?( vop_error ) + 2[ v os _a2 ] + ( i os )1000 ( r s _ref = 0 ?) t he differential output voltage error v o _error, dm, is the difference between vop_error and von_error: v o _error, dm = vop_error ? von_error (11) the output offset voltage of ea ch amplifier in the ada4941 - 1 also includes the effects of finite common - mode rejection ratio (cmrr) , power supply rejection ratio ( psrr ), and dc open - loop gain ( a vol ) . vol s cm os os a vout psrr v cmrr v _nom v v (12) w here: v os _nom is the nominal output offset voltage witho ut including the effects of cmrr, psrr, and a vol . indicates the cha nge in conditions from nominal . v cm is the input common - mode voltage (for a1, the voltage at in, and for a2 , the voltage at ref). v s is the power supply voltage . vout is either op amp output.
ada4941- 1 rev. c | page 17 of 24 table 7 , table 8 , and table 9 show typical error budgets for the circuits shown in figure 48, figure 49 , and figure 50. r f = 1.0 k? , r g = 4.99 k? , r s _in = 825 ?, r s _ref = 0 ? table 7 . output voltage error budget for g = 2.4 amplifier shown in figure 48 error source typical value vop_error von_error v o _dm_error v os _a1 0.1 mv + 0.12 mv ? 0 .12 mv +0 .24 mv i bp _a1 3 a + 2.48 mv ? 2.48 mv ? 4.96 mv i bn _a1 3 a ? 2.48 mv + 2.48 mv + 4.96 mv v os _a2 0.1 mv 0 mv + 0.2 mv + 0.2 mv tota l v o _error, dm = 0.44 mv r f = 0 ? , r g = , r s _in = 0 ? , r s _ref = 0 ? table 8 . output voltage error budget for amplifier shown in figure 49 error source typical value vop_error von_error v o _dm_error v os _a1 0.1 mv +0.1 mv ?0.1 mv +0.2 mv i bp _a1 3 a +2.48 mv ?2.48 mv ?4.96 mv i bn _a1 3 a ?2.48 mv +2.48 mv +4.96 mv v o s _a2 0.1 mv 0 mv +0.2 mv +0.2 mv tota l v o _ error , dm = 0 .4 mv r f = 1.02 k? , r g = 665 ?, r s _in = 402 ?, r s _ref = 0 ? table 9 . output voltage error budget for g = 5 amplifier shown in figure 50 error sourc e typical value vop_error von_error v o _dm_error v os _a1 0.1 mv +0.25 mv ?0.25 mv +0.5 mv i bp _a1 3 a +1.21 mv ?1.21 mv ?2.4 mv i bn _a1 3 a ?1.21 mv +1.21 mv +2.4 mv v os _a2 0.1 mv 0 mv +0.2 mv +0.2 mv tota l v o _error, dm = 0.7 mv output voltage noise 1k ? 1k ? r g r f r s ip ? a2 in ? a2 vn ? a1 500 ? a2 a1 ref in 2 8 4 5 fb out+ + ? vop 1 out? + ? von vn ? a2 r s? ref ip ? a1 in ? a1 05704-057 4kt (1k?) 4kt (1k?) 4kt (500?) 4kt ( r s? ref ) 4kt r s 4kt r g 4kt r f figure 52 . noise sources figure 52 shows the major contributors to the ada4941 - 1 differential output voltage noise . the differential output noise mean - square voltage equals the sum of twice the noise mea n - square voltage contributions from the noninverting channel (a1) , plus the noise mean - square voltage terms associated with the i nverting channel (a2). 2 2 2 2 2 2 2 2 _ 4 1 2 4 2 4 2 _ 2 ) _ ( 1 2 ) _ ( 1 2 _ , n von ktr r r r r ktr ktr r a1 in r a1 ip r r a1 vn r r n dm v s g f g f g f f s g f g f o u u u u u u u u (13) w here von_n 2 is calculated as ) ( 16 (500) 16 (1000) 8 ) _ ( 1000 ) _ 500 )( _ ( 4 4 2 2 2 2 _ref r kt kt kt a2 in ref r a2 ip vn_a2 von_n s s ( 1 4 ) w here : vn_a1 and vn_a2 are the input voltage noise s of a1 and a2, each equal to 2.1 nv/hz. in_a1 , in_a2 , ip_a1 , and ip_a2 are amplifier input cur rent noise terms, each equal to 1 pa/hz. r s , r f , and r g are the external source , feedback, and gain resistors , respectively . kt is boltzmanns constant times absolute temperature, equal to 4. 2 x 10 - 21 w - s at room tempera ture. r s _ref is any source resista nce at the ref pin. when a1 is used as a unity gain follower, the output voltage noise spectral density is at its minimum, 10 nv/hz. higher voltage gains have higher output voltage noise . table 10, tab le 11 , and table 12 show the noise contributions and output voltage noise for the circuits in figure 48, figure 49, and figure 50.
ada4941- 1 rev. c | page 18 of 24 table 10 . output voltage noise, g = 2.4 differential amplifier shown in figure 48 noise source typical value vop c ontribution ( nvhz) von c ontribution (nvhz) v o , dm contribution (nvhz) vn_a1 2.1 nv/hz 2.5 2.5 5 ip_a1 1 pa/hz 1 1 2 in_a1 1 pa/hz 1 1 2 4 k tr f 4 nv/hz 4 4 8 4 k tr g 9 nv/hz 1.8 1.8 3.6 4 k tr s 3.6 nv/hz 4.4 4.4 8.8 vn_inverter 9.2 nv/hz 0 9.2 9.2 r s _ref 0 0 0 0 ip_a2 r s _ref 0 0 0 0 totals 6.8 11.4 16.5 r f = 1.0 k? , r g = 4.99 k? , r s = 825 ? , r s _ref = 0 ? . vn_inverter = n oise contributions from a2 and its a ssociated internal 1 k? feedback resistors and 500 ? offset current balancing resistor. table 11 . output voltage noise, g = 2 differential a mplifier shown in figure 49 noise source typical value vop contribution (nvhz) von contribution (nvhz) v o , dm contribution (nvhz) vn_a1 2.1 nv/hz 2.1 2.1 4.2 ip_a1 0 0 0 0 in_a1 0 0 0 0 4 k tr f 0 0 0 0 4 k tr g 0 0 0 0 4 k tr s 0 0 0 0 vn_inverter 9.2 nv/hz 0 9.2 9.2 r s _ref 0 0 0 0 ip_a2 r s _ref 0 0 0 0 totals 2.1 9.4 10 r f = 0 ?, r g = , r s = 0 ?, r s _ref = 0 ? . table 12 . output voltage noise, g = 5 differential amplifier shown in figure 50 noise source typical value vop contribution (nvhz) von contr ibution (nvhz) v o , dm contribution (nvhz) vn_a1 2.1 nv/hz 5.25 5.25 10.5 ip_a1 1 pa/hz 1 1 2 in_a1 1 pa/hz 1 1 2 4 k tr f 4 nv/hz 4 4 8 4 k tr g 3.26 nv/hz 4.9 4.9 9.8 4 k tr s 2.54 nv/hz 6.54 6.54 13.1 vn_inverter 9.2 nv/hz 0 9.2 9.2 r s _ref 0 0 0 0 ip_a2 r s _ref 0 0 0 0 totals 10.7 14.1 23.1 r f = 1.02 k? , r g = 665 ?, r s = 402 ?, r s _ref = 0 ? .
ada4941- 1 rev. c | page 19 of 24 frequency response v s . closed - loop gain the operational amplifiers used in the ada4941 - 1 are voltage feedback with an open - loop frequency response that can be approximated with the integrator response , as shown in figure 53. 100 0 0.001 100 frequency (mhz) open-loop gain (db) 05704-062 80 60 40 20 0.01 0.1 1 10 fcr = 50mhz figure 53 . ada4941 - 1 op a mp open - loop gain vs. frequency for each amplifier, the frequency response can be approximated by the following equations: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + = fcr f r r r r r vin _a1 v g g f g f o 1 1 1 (15 ) (noninverting response) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? = fcr f r r r r r vin _a2 v g g f g f o 1 1 (1 6 ) (inverting r esponse) f cr is the gain - bandwidth frequency o f the amplifier (where the open - loop gain shown in figure 53 equals 1) . f cr for both amplifiers is about 50 mhz. the inverting amplifier a2 has a fixe d feedback network . the transfer function is approximately ? ? ? ? ? ? ? ? ? ? ? ? + ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? = mhz 25 1 1 mhz 50 2 1 1 2 _ f vop f vin a v o ( 17) a1s frequency response depend s on the external feedback network as indicated by equation 15. the overall differential output voltage is therefore v o , dm = vop ? von = vop + vop ? ? ? ? ? ? ? ? ? ? ? ? + mhz 25 1 1 f (18) ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + = mhz 25 1 1 1 mhz 50 1 1 1 f f r r r r r vin , dm v g g f g f o (19 ) multiplying the terms and neglecting negligible terms leads to the following approximation: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + = mhz 25 1 mhz 50 1 2 1 , f f r r r r r vin dm v g g f g f o (2 0 ) there are two poles in this transfer function , and the lower freq uency pole limits the bandwidth of the differential amplifier . if vop is shorted to in ? (a1 is a unity gain follower), the 25 mhz closed - loop bandwidth of the inverting channel limits the overall bandwidth . when a1 is operating with higher noise gains, the bandwidth is limited by a1s closed - loop bandwidth , which is inversely proportional to the noise gain (1 + r f /r g ) . for instance, if the external feedback network provides a noise gain of 10, the bandwidth drop s to 5 mhz.
ada4941- 1 rev. c | page 20 of 24 applications overview the ada49 41 - 1 is an adjustable - gain , single - ended - to - differential voltage amplifier, optimized for driving high resolution adcs. single - ended - to - differential gain is controlled by one feedback network, comprised of two external resistors: r f and r g . using the ref p in the ref pin sets the output base line in the inverting path and is used as a reference for the input signal . in most applications , the ref pin is set to the input signal mid swing level, which in many cases is also mid supply . for bipolar signals and dual power supplies, ref is generally set to ground . in single - supply applications, sett ing ref to the input signal mid swing level provides optimal output dynamic range performance with minimum differential offset . n ote that the ref input only affects the inve rting signal path or von . most applications require a differential output signal with the same dc common - mode level on each output . it is possible for the signal measured across vop and von to have a common - mode voltage that is of the desired level but not common to both outputs . this type of signal is generally avoided because it does not allow for optimal use of the amplifiers output dynamic range . defining v in as the voltage applied to the input pin, the equations that govern the two signal paths are g iven in equation 2 1 and equation 2 2 . vop = vin (2 1 ) von = ? vin + 2 ( ref ) (2 2 ) when th e ref voltage is set to the mid swing level of the input signal, the two output signals fall directly on top of each other with minimal offset . setting the ref voltage else where results in an offset bet ween the two outputs. the best use of the ref pin can be further illustrated by considering a single - supply case with a 10 v power supply and an in put signal that varies between 2 v and 7 v . this is a case where the mid swing level of the input signal is not at midsupply but is at 4.5 v . setting the ref input at 4.5 v and neglecting offsets, equation 2 1 and equation 2 2 are used to calculate the results . when the inpu t signal is at its midpoint of 4.5 v, out+ is at 4.5 v, as is von . this can be considered as a base line state where the differential output voltage is 0. when the input increases to 7 v, vop tracks the input to 7 v , and von decreases to 2 v . this can be viewed as a positive peak signal where the diff erential output voltage equals 5 v . when the input signal decreases to 2 v, vop again tracks to 2 v, a n d von increases to 7 v . this can be viewed as a negative peak signal where the differential output voltage equals ? 5 v . the resulting differential output voltage is 10 v p - p . the previous discussion reveals how the single - ended - to - differential gain of 2 is achieved. internal feedback ne twork power dissipation while traditional op amps do not have on - chip feedback elements, the ada49 41- 1 contains two on - chip , 1 k? resisto rs that comprise an internal feedback loop . the power dissipated in these resistors must be included in the overall power dissipation calculations for the device . under certain circumstances, the power dissipated in these resistors could be comparable to t he devices quiescent dissipation . for example, on 5 v supplies with the ref pin tied to ground and out ? at + 4 vdc, each 1 k? resistor carries 4 ma and dissipates 1 6 mw for a total of 32 mw . this is comparable to the quiescent power and must therefore be included in the overall device power dissipation calculations . for ac signals, rms analysis is required. disable feature the ada4941 - 1 includes a disable feature that can be asserted to minimize power consumption in a device that is not needed at a particu lar time . when asserted, the disable feature does not place the device output in a high impedance or t ri s tate condition . the disable feature is active high . see the specifications tables for the high and low level voltage specifi cations.
ada4941- 1 rev. c | page 21 of 24 adding a 3 - pole , s a llen - key filter the non inverting amplifier in t he ada4941 - 1 can be used as the buffer amplifier of a sallen - key filter . a 3 - pole , low - pass filter can be designed to limit the signal bandwidth in front of an adc . the input si gnal first passes through the noninverting s tage where it is filtered . the filtered signal is then passed through the inverting stage to obtain the complementary output. figure 54 illustrates a 3 - pole , sallen - key , low - pass filter with a ? 3 db cutoff frequency of 100 k hz . the 1.69 k? resistor is included to minimize dc errors due to the input offset current in a1 . the passive rc filters on the output s are generally required by the adc converter that is being driven . the frequency r esponse of the filter is shown in figure 55. 1k ? 1k ? 500 ? a2 a1 ref in 2 8 4 2.7nf 5 fb +5v ?5v 560pf v s+ v s? out+ + ? v o, dm 1 3 out? vin 562 ? 562 ? 562 ? 1.69k ? 33 ? 33 ? 6 05704-058 0.1 f 0.1 f 2.7nf 3.9nf 10nf figure 54 . sallen - key, low - p ass filter with 100 k hz cutoff frequency 0 ?100 10 100m frequency (hz) v o, dm /vin ( db ) 05704-059 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 100 1k 10k 100k 1m 10m v o, dm = 3v p-p figure 55 . frequency response of the circuit shown in figure 54
ada4941- 1 rev. c | page 22 of 24 driving the ad7687 a dc the ada4941 - 1 is an excellent driver for high resol ution adcs , such a s the ad7687 , a s shown in fi gure 56 . the sallen - key , low - pass filter shown in figure 54 is included in this example but is not required. the circuit shown in figure 56 accepts single - ended input signals that swing between 0 v and 3 v . th e adr443 provides a stable, low noise , 3 v reference that is buffered by one of the ad8032 amplifi ers and applied to the ad7687 ref input, providing a differential input full - scale level of 6 v . the reference voltage is also divided by two and buffered to supply the midsupply re f level of 1.5 v for the ada4941 - 1. gain of ?2 configura tion the ada4941 - 1 can be operated in a configuration referred to as gain of ?2. clearly, a gain of ?2 can be achieved by simply swapping the outputs of a gain of +2 circuit, but the configuration described here is different. the configuration is referred to as having negative gain to emphasize that the input amplifier, a1, is operated as an inverting amplifier instead of in its usual noninverting mode. as implied in its name, the voltage gain from vin to v o , dm is ? 2 v / v. see figure 57 for t he gain of ?2 configuration on 5 v supplies . the gain of ? 2 configuration is most useful in applications that have wide input swings because the input common - mode voltage s are held at constant level s . the signal size is therefore constrained by the output swing limits. the gain of ? 2 has a low input resistance that is equal to r g . 1k ? 1k ? gnd 500 ? a2 a1 ada4941-1 ref in in+ in? 2 8 4 2.7nf 5 fb +5v +5v ?5v 560pf v s+ v s? out+ 1 3 out? v in vin 0v to 3v v out 562 ? 562 ? 562 ? 1.69k ? 33 ? 33 ? 6 05704-060 0.1 f 0.1 f 10 f 2.7nf 3.9nf 10nf 1/2 ad8032 adr443 4 8 1 4 0.1 f 0.1 f 3 3 4 2 6 2 1/2 ad8032 ad7687 7 5 6 +5v 1k ? 1k ? 10 f 10 f 0.1 f 0.1 f vdd gnd 5 ref 1 2 figure 56 . ada4941 - 1 driving the ad7687 adc 1k ? 1k ? r f 1k ? r g 1k ? 500 ? 500 ? a2 a1 ref in 2 8 4 5 fb +5v ?5v v s+ v s? out+ 1 3 6 out? vin 05704-061 + ? v o, dm figure 57 . gain of ?2 configuration
ada4941- 1 rev. c | page 23 of 24 outline dimensions contr ollin g dimen sions are in millimeters; inch dimension s (in p aren the ses) are round ed-of f milli mete r equiv alents for r efere nce onl y and are not appro pria te for use in des ign. compl iant t o jedec st andards ms-012-aa 012407 -a 0.25 (0.00 98) 0.17 (0.00 67) 1.27 (0.05 00) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.00 99) 45 8 0 1.75 (0.0688) 1.35 (0.05 32) sea ting plane 0.25 (0.00 98) 0.10 (0.00 40) 4 1 8 5 5.00 (0.19 68) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.14 97) 1.27 (0.0500) bsc 6.20 (0.24 41) 5.80 (0.2284) 0.51 (0.020 1) 0.31 (0.0122) copla narit y 0.10 figure 58 . 8- lead standard small outline package [soic _n ] narrow body (r - 8) dimensions shown in millimeters and (inches ) 090308-b 1 exposed p ad (bot t om view) 0.50 bsc pin 1 indic a t or 0.50 0.40 0.30 t o p view 12 max 0.70 max 0.65 ty p 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indic a t or sea ting plane 0.30 0.23 0.18 0.60 max 0.60 max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 59 . 8- lead lead fr ame chip scale package [lfcsp _vd ] 3 mm 3 mm body , very thin, dual lead (cp - 8 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering q uan t ity branding ada4941 - 1yrz ? 40c to +125c 8 - lead soic_ n r -8 98 ada4941 - 1yrz -rl ? 40c to +125c 8 - lead soic_n r -8 2 , 500 ada4941 - 1yrz -r7 ? 40c to +125c 8 - lead soic_n r -8 1 , 000 ada4941 - 1ycpz - r2 ? 40c to +125c 8 - lead lfcsp_vd cp - 8 - 2 250 h0c ada4941 - 1ycpz -rl ? 40c to +125c 8 - lead lfcsp_vd cp -8 -2 5 , 000 h0 c ada4941 - 1ycpz -r7 ? 40c to +125c 8 - lead lfcsp_vd cp -8 -2 1 , 500 h0c ada4941 - 1ycp - ebz evaluation board ada4941 - 1yr - ebz evaluation board 1 z = rohs compliant part.
ada4941- 1 rev. c | page 24 of 24 notes ? 2006 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05704 - 0 - 8/11(c)

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